Challenges in scaling memory bandwidth in modern SoCs by Nithya Bashyam

Abstract: Memory bandwidth scaling has emerged as a critical bottleneck as compute capabilities continue to grow faster than DRAM performance. This talk examines why higher memory frequencies do not directly translate to higher delivered bandwidth, focusing on bandwidth efficiency rather than peak bandwidth. It discusses key constraints arising from DRAM organization, timing parameters, power, reliability and security, and highlights the roles of memory controllers, SoC architecture, and workload behavior. The talk provides a framework to understand the architectural trade‑offs involved in sustaining memory bandwidth scaling in modern SoCs.

Biography: A Principal Engineer in Client SoC Performance Architecture at Intel, Nithya Bashyam holds an M.Tech. in Electronics Design from CEDT, IISc. He joined Intel in 2004, initially working on front‑end design for two years, before moving in 2006 to the CPU SoC Architecture team. He contributed to the industry’s first CPU with integrated graphics and memory controller on Sandy Bridge, released in 2011, followed by work on a few generations of server CPUs. Since Skylake (2015), he has focused on client CPUs, working across the core‑to‑memory path including cache, ring, memory controllers, and aspects of the I/O subsystem. He has led memory subsystem performance for several generations of client SoCs and led SoC performance for Lunar Lake (2024) and Panther Lake (2025).