4 credits (3-0-2)
Pre-requisites: COL215 OR Equivalent
After a basic overview of the VLSI design flow, hardware modelling principles and hardware description using the VHDL language are covered. This is followed by a study of the major steps involved in behavioural synthesis: scheduling, allocation, and binding. This is followed by register-transfer level synthesis, which includes retiming and Finite State Machine encoding. Logic synthesis, consisting of combinational logic optimisation and technology mapping, is covered next. Popular chip architectures – standard cells and FPGA are introduced. The course concludes with a brief overview of layout synthesis topics: placement and routing.