The group has interests in Hardware-software co-design, Embedded systems design, Reconfigurable computing, Fault-tolerant computing, Hardware implementations, Temperature-aware architectures, Energy-efficient architectures, Design-for-debug, Cache memory, 3D and non-volatile memory, Architectural extensions for mobile security, Architectures for machine learning, Architectures for computer vision, Secure architectures.
Publications
3D-TemPo: Optimizing 3-D DRAM Performance Under Temperature and Power Constraints Journal Article
In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., vol. 43, no. 8, pp. 2263–2276, 2024.
NOVELLA: Nonvolatile Last-Level Cache Bypass for Optimizing Off-Chip Memory Energy Journal Article
In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., vol. 43, no. 11, pp. 3913–3924, 2024.
COBRRA: COntention-aware cache Bypass with Request-Response Arbitration Journal Article
In: ACM Trans. Embed. Comput. Syst., vol. 23, no. 1, pp. 12:1–12:30, 2024.
NeuroTAP: Thermal and Memory Access Pattern-Aware Data Mapping on 3D DRAM for Maximizing DNN Performance Journal Article
In: ACM Trans. Embed. Comput. Syst., vol. 23, no. 6, pp. 96:1–96:30, 2024.
APPAMM: Memory Management for IPsec Application on Heterogeneous SoCs Proceedings Article
In: 32nd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2024, Tanger, Morocco, October 6-9, 2024, pp. 1–6, IEEE, 2024.
Members
